✝️ 1 Corinthians 14:20 Brothers and sisters, do not be children in your thinking; rather, be infants in evil, but in thinking be adults. ![[AARCH64_NEIGHBORHOOD.png]] # WELCOME TO THE AARCH64 NEIGHBORHOOD Howdy neighbor! I see you just moved to the `AARCH64` neighborhood. My name is stackpointer but you can call me SP, I am a member of the registers family! Before you get settled in I will tell you about this neighborhood and some additional information and then you will meet some families in this neighborhood. # The syntax used in this document most likely differs from the ARM ARM. * ## The destination register is the register being written to. * ## When I refer to type I mean if something is either a 64 bit register or the lower 32 bits of a 64 bit register. * ## The source register is the register being read from. * ## Rd := Destination register. * ## Rs := Source register. * ## Rsd := Register that is both read from and written to. * ## roi := Register or immediate. * ## imm := Immediate. * ## label := PC relative or literal address to jump to. * ## cond := condition. * ## smf := Source modifier, may be optional or not. * ## m := The size of the destination register in bits or if the instruction has no destination register then the size of the first source register in bits, either 32 or 64. * ## {...} := Optionally pick whatever is in {}. * ## (...) := Required, pick whatever is in (). * ## A|B := Pick either A or B. * ## Optional or required stuff may contain stuff like (A|B) or {A|B}, for the required section you must pick either A or B, for the optional section you must select A, B, or nothing. * ## There can be multiple destination and source registers, written like: Rd1, Rd2, Rd3, etc for destination register and like this for source registers: Rs1, Rs2, Rs3, etc. There can also be multiple Rsds, written like: Rsd1, Rsd2, Rsd3, etc. There can be multiple immediate numbers, written like: imm1, imm2, imm3, etc. There can be multiple rois written like: roi1, roi2, roi3, etc. # Some facts about the AARCH64 neighborhood * ## AARCH64 has 31 64 bit general purpose registers (from X0 to X30, and W0 to W30 to refer to the lower 32 bits of them) because the instruction encoding uses 5 bits for each register and that can encode (0-31). Now, register 31 is used to either encode the zero register (XZR for the 64 bit form or WZR to refer to the lower 32 bits) or the stackpointer (me! SP for the 64 bit form and WSP for the lower 32 bits) depending on the instruction. * ## Even though AARCH64 has 31 general purpose registers, X30 (W30 being the lower 32 bits) is used as the link register. * ## AARCH64 has PC, that is a register that points to the current instruction to be executed. The PC steps in intervals of 4 so the next instruction to be ran would be PC + 4 unless a branch occurs. * ## NZCV are condition flags that refer to the negative, zero, carry, and overflow flag. * ## The negative flag is set if bit m - 1 of the result is 1. * ## The zero flag is set if the result is 0. * ## The carry flag is set for addition if unsigned result did not fit in m bits. It's set for subtraction if no unsigned underflow happened. * ## The overflow flag is set if a signed overflow occurred. * ## Writing to the lower 32 bits of a register (W7 as an example), zeros the upper 32 bits of the register. * ## Some instructions end with S meaning they set NZCV. # The possible values for cond are: * ## EQ * ## The zero flag is 1. * ## NE * ## The zero flag is 0. * ## CS * ## The carry flag is 1. * ## HS * ## The carry flag is 1. * ## CC * ## The carry flag is 0. * ## LO * ## The carry flag is 0. * ## MI * ## The negative flag is 1. * ## PL * ## The negative flag is 0. * ## VS * ## The overflow flag is 1. * ## VC * ## The overflow flag is 0. * ## HI * ## The carry flag is 1 and the zero flag is 0. * ## LS * ## The carry flag is 0 or the zero flag is 1. * ## GE * ## The negative flag equals the overflow flag. * ## LT * ## The negative flag does not equal the overflow flag. * ## GT * ## The zero flag is 0 and the negative flag equals the overflow flag. * ## LE * ## The zero flag is 1 or the negative flag does not equal the overflow flag. * ## AL * ## Always. * ## NV * ## Always. # Some instructions have the ability to modify the value of a source operand before using it. Note that this modifier is a part of the instruction, not a separate instruction, and also note that the source operand itself is not being modified. The possible modifiers are: * ## LSL imm1 * ### Shifts the source operand to the left by imm1 bits and the low bits are set to zero and the high bits are lost. * ## LSR imm * ### Shifts the source operand to the right by imm1 bits and the high bits are set to zero and the low bits are lost. * ## ASR imm1 * ### Shifts the source operand to the right by imm1 bits and the high bits are set to the sign bit and the low bits are lost. * ## ROR imm1 * ### Shifts the source operand to the right by imm1 bits and the bits wrap around so no bits are lost. * ## UXTB imm1 * ### Zero extend the lowest byte of the source operand and then shift left by imm1 bits. * ## UXTH imm1 * ### Zero extend the lowest 2 bytes of the source operand and then shift left by imm1 bits. * ## UXTW imm1 * ### Zero extend the lowest 4 bytes of the source operand and then shift left by imm1 bits. * ## UXTX imm1 * ### Zero extend the whole source operand and then shift left by imm1 bits. * ## SXTB imm1 * ### Sign extend the lowest byte of the source operand and then shift left by imm1 bits. * ## SXTH imm1 * ### Sign extend the lowest 2 bytes of the source operand and then shift left by imm1 bits. * ## SXTW imm1 * ### Sign extend the lowest 4 bytes of the source operand and then shift left by imm1 bits. * ## SXTX imm1 * ### Sign extend the whole source operand and then shift left by imm1 bits. # Time to meet the families! Now that you have learned some facts about this place, it's time I introduce you to some of the families living here. # The Mov family ## The Mov family has been living in this neighborhood for a long time, they have hosted the usual activities such as the annual intel assault and the classic ARM wrestling contest more than any other family. * ## MOV(Z|N|K) Rd1, imm1, smf * ## Rd1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. If rd1 is a 64 bit general purpose register then smf can be LSL 0, LSL 16, LSL 32, or LSL 48. If rd1 is the lower 32 bits of a 64 bit general purpose register smf can be LSL 0 or LSL 16. Note that imm1 can be 0 to 65535. * ## Rd1 is set to smf applied to imm1 and if the instruction ends with Z then the other bits are set to 0, if the instruction ends with N then a bitwise NOT is performed on every bit in smf applied to imm1, if the instruction ends with K then the other bits are unchanged. # The Arithmetic family ## The Arithmetic family is mainly in charge of the annual spending of the entire neighborhood and makes sure no family spends to much money, and if they do they get deprecated. * ## ADD{S} Rd1, Rs1, roi1, smf * ## smf is optional here, if it is not used it is equal to LSL 0. If smf is LSL imm1 then imm1 is equal to 0 or 12 and Rd1 and Rs1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register and roi1 can be 0 to 4095. Rs1 can be also SP or WSP and if the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. Rd1 and Rs1 must share the same type. * ## smf is optional here, if it is not used it is equal to LSL 0. If smf is either LSL imm1, LSR imm1, or ASR imm1 then imm1 is equal to 0 to m - 1 and Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register, they can also be XZR or WZR. Rd1, Rs1, and roi1 must share the same type. * ## smf is required here. If smf is either UXTB {imm1}, UXTH {imm1}, UXTW {imm1}, SXTB {imm1}, SXTH {imm1}, or SXTW {imm1} then imm1 is equal to 0 to 4, imm1 is optional here, if it is not used it is equal to 0. Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register while roi1 must be the lower 32 bits of a 64 bit general purpose register. Rs1 can also be SP or WSP and roi1 can also be WZR. Rd1 and Rs1 must share the same type. If the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. * ## smf is required here. If smf is either UXTX {imm1} or SXTX {imm1} then imm1 is equal to 0 to 4, imm1 is optional here, if it is not used it is equal to 0. Rd1, Rs1, and roi1 can be any 64 bit general purpose register. Rs1 can also be SP and roi1 can also be XZR. If the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. * ## Rd1 is set to Rs1 plus the result of smf applied to roi1. If the instruction ends with the optional S then NZCV is set. * ## SUB{S} Rd1, Rs1, roi1, smf * ## smf is optional here, if it is not used it is equal to LSL 0. If smf is LSL imm1 then imm1 is equal to 0 or 12 and Rd1 and Rs1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register and roi1 can be 0 to 4095. Rs1 can be also SP or WSP and if the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. Rd1 and Rs1 must share the same type. * ## smf is optional here, if it is not used it is equal to LSL 0. If smf is either LSL imm1, LSR imm1, or ASR imm1 then imm1 is equal to 0 to m - 1 and Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register, they can also be XZR or WZR. Rd1, Rs1, and roi1 must share the same type . * ## smf is required here. If smf is either UXTB {imm1}, UXTH {imm1}, UXTW {imm1}, SXTB {imm1}, SXTH {imm1}, or SXTW {imm1} then imm1 is equal to 0 to 4, imm1 is optional here, if it is not used it is equal to 0. Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register while roi1 must be the lower 32 bits of a 64 bit general purpose register. Rs1 can also be SP or WSP and roi1 can also be WZR. Rd1 and Rs1 must share the same type. If the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. * ## smf is required here. If smf is either UXTX {imm1} or SXTX {imm1} then imm1 is equal to 0 to 4, imm1 is optional here, if it is not used it is equal to 0. Rd1, Rs1, and roi1 can be any 64 bit general purpose register. Rs1 can also be SP and roi1 can also be XZR. If the instruction ends with the optional S then Rd1 can also be XZR or WZR, if the instruction does not end with the optional S then Rd1 can also be SP or WSP. * ## Rd1 is set to Rs1 minus the result of smf applied to roi1. If the instruction ends with the optional S then NZCV is set. * ## ADC{S} Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be a 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## Rd1 is set to Rs1 plus Rs2 plus the carry flag and if the optional S is at the end of the instruction NZCV is set. * ## SBC{S} Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## Rd1 is set to Rs1 minus Rs2 minus 1 plus the carry flag and if the optional S is at the end of the instruction NZCV is set. * ## M(ADD|SUB) Rd1, Rs1, Rs2, Rs3 * ## Rd1, Rs1, Rs2, and Rs3 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## Rd1 is set to the product of Rs1 and Rs2 plus Rs3 if the instruction ends with ADD, if the instruction ends with SUB then Rd1 is set to Rs3 minus the product of Rs1 and Rs2. * ## (S|U)MULH Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or XZR. * ## If the instruction starts with S then Rd1 is set to the high 64 bits of Rs1 and Rs2 both treated as signed numbers and multiplied against each other, if the instruction starts with U then Rd1 is set to the high 64 bits of Rs1 and Rs2 both treated as unsigned numbers and multiplied against each other. * ## (S|U)M(ADD|SUB)L Rd1, Rs1, Rs2, Rs3 * ## Rd1 and Rs3 can be any 64 bit general purpose register or XZR while Rs1 and Rs2 can be the lower 32 bits of a 64 bit general purpose register or WZR. * ## Rd1 is set to Rs3 plus the product of Rs1 and Rs2, if the instruction ends with ADDL or minus the product of Rs1 and Rs2 if the instruction ends with SUBL. Both Rs1 and Rs2 will either be sign extended if the instruction starts with S or zero extended if the instruction starts with U. * ## (S|U)DIV Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## Anything divided by 0 is set to 0. * ## If the instruction starts with S then the smallest signed integer divided by -1 is set to the smallest signed integer. * ## Division truncates towards 0. * ## Rd1 is set to Rs1 divided by Rs2, with both numbers being unsigned if the instruction starts with U or signed if the instruction starts with S. * ## ADDPT Rd1, Rs1, Rs2, \<smf> * ## SUBPT Rd1, Rs1, Rs2, \<smf> * ## MADDPT Rd1, Rs1, Rs2, Rs3 * ## MSUBPT Rd1, Rs1, Rs2, Rs3 # The Logic family ## The Logic family hosts the annual processor modeling contest where each family has to model the entire MIPS architecture with classic logic and sets. * ## AND{S} Rd1, Rs1, roi, smf * ## smf is optional here, if it is not used then it is equal to LSL 0. If smf is LSL imm1, LSR imm1, ASR imm1, ROR imm1, and imm1 is 0 to m - 1 then Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. They all can also be either XZR or WZR. They must be the same type. * ## If no smf is used and roi1 is not a register then Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. Rs1 can also be XZR or WZR. Rd1 can also be SP or WSP if the instruction does not end with S but if the instruction does end with S Rd1 can also be XZR or WZR. Rd1 and Rs1 must be the same type. Now, roi1 must be a chunk repeated to fill m bits of a register, where the chunk is 2, 4, 8, 16, 32, or 64 bits wide and its 1 bits form an unbroken chain. * ## Rd1 is set to the result of the bitwise AND operation between Rs1 and the result of smf applied to roi1 if smf exists, if not just roi1. If the instruction ends with the optional S then NZCV is set. * ## ORR Rd1, Rs1, roi, smf * ## smf is optional here, if it is not used then it is equal to LSL 0. If smf is LSL imm1, LSR imm1, ASR imm1, ROR imm1, and imm1 is 0 to m - 1 then Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. They all can also be either XZR or WZR. They must be the same type. * ## If no smf is used and roi1 is not a register then Rd1 and Rs1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. Rs1 can also be XZR or WZR. Rd1 can also be SP or WSP. Rd1 and Rs1 must be the same type. Now, roi1 must be a chunk repeated to fill m bits of a register, where the chunk is 2, 4, 8, 16, 32, or 64 bits wide and its 1 bits form an unbroken chain. * ## Rd1 is set to the result of the bitwise OR operation between Rs1 and the result of smf applied to roi1 if smf exists, if not just roi1. * ## EOR Rd1, Rs1, roi, smf * ## smf is optional here, if it is not used then it is equal to LSL 0. If smf is LSL imm1, LSR imm1, ASR imm1, ROR imm1, and imm1 is 0 to m - 1 then Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. They all can also be either XZR or WZR. They must be the same type. * ## If no smf is used and roi1 is not a register then Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. Rs1 can also be XZR or WZR. Rd1 can also be SP or WSP. Rd1 and Rs1 must be the same type. Now, roi1 must be a chunk repeated to fill m bits of a register, where the chunk is 2, 4, 8, 16, 32, or 64 bits wide and its 1 bits form an unbroken chain. * ## Rd1 is set to the result of the bitwise XOR operation between Rs1 and the result of smf applied to roi1 if smf is used, if not just roi1. * ## ORN Rd1, Rs1, Rs2, smf * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## smf can be LSL imm1, LSR imm1, ASR imm1, or ROR imm1. imm1 can be 0 to m - 1. * ## Rd1 is set to the result of the bitwise OR NOT operation between Rs1 and the result of smf applied to Rs2. * ## EON Rd1, Rs1, Rs2, smf * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## smf can be LSL imm1, LSR imm1, ASR imm1, or ROR imm1. imm1 can be 0 to m - 1. * ## Rd1 is set to the result of the bitwise XOR NOT operation between Rs1 and the result of smf applied to Rs2. * ## BIC{S} Rd1, Rs1, Rs2, smf * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of a general purpose register, they can also be XZR or WZR. They must be the same type. * ## smf can be LSL imm1, LSR imm1, ASR imm1, or ROR imm1. imm1 can be 0 to m - 1. * ## Rd1 is set to the result of the bitwise AND NOT operation between Rs1 and the result of smf applied to Rs2 and NZCV is set if the instruction ends with the optional S. # The Shiftv family ## The Shiftv family decides which families host the annual intel assault and ARM wrestling contest. * ## LSLV Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be the XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 shifted to the left by Rs2 MOD m. * ## LSRV Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be the XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 shifted to the right by Rs2 MOD m. * ## ASRV Rd1, Rs1, Rs2 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be the XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 shifted to the right by Rs2 MOD m and the bits from m - 1 to m - Rs2 MOD m of Rd1 are set to copies of Rs1's sign bit. * ## RORV Rd1, Rs1, Rs2 ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be the XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 rotated to the right by Rs2 MOD m and bits that fall off the right come back in on the left # Shiftv family aliases * ## LSL Rd1, Rs1, Rs2 * ## LSLV Rd1, Rs1, Rs2 * ## LSR Rd1, Rs1, Rs2 * ## LSRV Rd1, Rs1, Rs2 * ## ASR Rd1, Rs1, Rs2 * ## ASRV Rd1, Rs1, Rs2 * ## ROR Rd1, Rs1, Rs2 * ## RORV Rd1, Rs1, Rs2 # The BFM family ## The BFM family loves to help out around the neighborhood such as with electrical work and maintenance. * ## {S|U}BFM Rd1, Rs1, imm1, imm2 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be the XZR or WZR. They must share the same type. * ## Both imm1 and imm2 must be 0 to m - 1. * ## If imm2 is greater than or equal to imm1 then the range of bits from imm1 through imm2 in Rs1 are copied into Rd1 starting at bit 0. If the instruction does not start with S or U then the bits outside the range stay the same, if the instruction starts with S then the bits outside the range are set to bit imm2 of Rs1, if the instruction starts with U then the bits outside the range are set to 0. * ## If imm1 is greater than imm2 then, imm2 + 1 bits are copied from Rs1 starting at the lowest bit into Rd1 at bit position m - imm1. The bits outside of the range stay the same if the instruction does not start with S or U, if the instruction starts with S then the bits above are set to bit imm2 of Rs1 while the lower bits are set to 0, if the instruction starts with U then the bits outside the range are set to 0. ## BFM family member aliases * ## BFM * ## BFI Rd1, Rs1, imm1, imm2 * ## BFM Rd1, Rs1, -imm1 MOD m, imm2 - 1 * ## BFXIL Rd1, Rs1, imm1, imm2 * ## BFM Rd1, Rs1, imm1, imm1 + imm2 - 1 * ## UBFM * ## LSL Rd1, Rs1, imm1 * ## UBFM Rd1, Rs1, -imm1 MOD m, m - imm1 - 1 * ## LSR Rd1, Rs1, imm1 * ## UBFM Rd1, Rs1, imm1, m - 1 * ## UXTB Rd1, Rs1 * ## UBFM Rd1, Rs1, 0, 7 * ## UXTH Rd1, Rs1 * ## UBFM Rd1, Rs1, 0, 15 * ## UBFX Rd1, Rs1, imm1, imm2 * ## UBFM Rd1, Rs1, imm1, imm1 + imm2 - 1 * ## UBFIZ Rd1, Rs1, imm1, imm2 * ## UBFM Rd1, Rs1, -imm1 MOD m, imm2 - 1 * ## SBFM * ## ASR Rd1, Rs1, imm1 * ## SBFM Rd1, Rs1, imm1, m - 1 * ## SXTB Rd1, Rs1 * ## SBFM Rd1, Rs1, 0, 7 * ## SXTH Rd1, Rs1 * ## SBFM Rd1, Rs1, 0, 15 * ## SXTW Rd1, Rs1 * ## For this alias Rd1 and Rs1 have to be a full 64 bit register and not the lower 32 bits. * ## SBFM Rd1, Rs1, 0, 31 * ## SBFX Rd1, Rs1, imm1, imm2 * ## SBFM Rd1, Rs1, imm1, imm1 + imm2 - 1 * ## SBFIZ Rd1, Rs1, imm1, imm2 * ## SBFM Rd1, Rs1, -imm1 MOD m, imm2 - 1 # The Bitmanipulation family ## The Bitmanipulation family are really good at spotting details such if your fence is an inch to close to their house. * ## CL(Z|S) Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## If the instruction ends with Z then Rd1 is set to the number of 0 bits starting from bit m - 1 going to bit 0, before the first 1 bit in Rs1. If Rs1 is 0 then Rd1 will be set to m. If the instruction ends with S then Rd1 is set to the number of bits that are equal to bit m - 1 starting at bit m - 2 going to bit 0, before the first bit that does not match in Rs1. If all bits in Rs1 are equal to bit m - 1 then Rd1 will be equal to m - 1. * ## RBIT Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 in a reversed bit order. * ## REV{16|32} Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 in a reversed byte order if the instruction does not end in 16 or 32 but if the instruction ends with 16 then Rd1 is set to Rs1 with every interval of 2 bytes swapped. If the instruction ends with 32 then Rd1 is set to Rs1 with every interval of 4 bytes swapped. * ## CNT Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to the amount of bits equal to 1 in Rs1. * ## ABS Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to the signed absolute value of Rs1. * ## (S|U)MIN Rd1, Rs1, roi1 * ## Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. Rd1 and Rs1 must share the same type and roi1 must share the same type as well if it is a register but it can also be -128 to 127 if the instruction starts with S or 0 to 255 if the instruction starts with U. * ## Rd1 is set to whatever is smaller between Rs1 and roi1 both being treated as signed numbers if the instruction starts with S or unsigned numbers if the instruction starts with U, if Rs1 and roi1 are equal Rd1 is set to be equal to them. * ## (S|U)MAX Rd1, Rs1, roi1 * ## Rd1, Rs1, and roi1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. Rd1 and Rs1 must share the same type and roi1 must share the same type as well if it is a register but it can also be -128 to 127 if the instruction starts with S or 0 to 255 if the instruction starts with U. * ## Rd1 is set to whatever is bigger between Rs1 and roi1 both being treated as signed numbers if the instruction starts with S or unsigned numbers if the instruction starts with U, if Rs1 and roi1 are equal Rd1 is set to be equal to them. * ## CTZ Rd1, Rs1 * ## Rd1 and Rs1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to the number of 0 bits starting from the right going to the left before a 1 bit in Rs1. If Rs1 is 0 then Rd1 will be set to m. * ## EXTR Rd1, Rs1, Rs2, imm1 * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## imm1 can be 0 to m - 1. * ## Rd1 is set to m bits starting at bit imm1 of Rs2, going into Rs1. # The Condition family ## The Condition family is the family that always starts drama. * ## CSEL Rd1, Rs1, Rs2, cond * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 if cond is true and Rs2 if it is false. * ## CSINC Rd1, Rs1, Rs2, cond * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 if cond is true and Rs2 + 1 if it is false. * ## CSINV Rd1, Rs1, Rs2, cond * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 if cond is true and the result of the bitwise not operation on Rs2 if it is false. * ## CSNEG Rd1, Rs1, Rs2, cond * ## Rd1, Rs1, and Rs2 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type. * ## Rd1 is set to Rs1 if cond is true and the two's complement negation of Rs2 if it is false. * ## CCMP Rs1, roi1, imm1, cond * ## Rs1 and roi1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type if they are both registers, but roi1 can also be 0 to 31. * ## imm1 can be 0 to 15. * ## If cond is true then NZCV is based on the result of Rs1 - roi1, if cond is false then NZCV is set to imm1. * ## CCMN Rs1, roi1, imm1, cond * ## Rs1 and roi1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type if they are both registers, but roi1 can also be 0 to 31. * ## imm1 can be 0 to 15. * ## If cond is true then NZCV is based on the result of Rs1 + roi1, if cond is false then NZCV is set to imm1. # The Branch family ## The Branch family is the family that always helps clearing trees that fall down. * ## B label * ## If label is less than or equal to 128 megabytes away from PC then PC is set to label. * ## B.cond label * ## If label is less than or equal to 1 megabyte away from PC and cond is true then PC is set to label. * ## BL label * ## If label is less than or equal to 128 megabytes away from PC then X30 is set to 4 bytes after the PC, and PC is set to label. * ## BR Rs1 * ## Rs1 can be a 64 bit general purpose register or XZR. * ## PC is set to Rs1. * ## BLR Rs1 * ## Rs1 can be a 64 bit general purpose register or XZR. * ## X30 is set 4 bytes after PC, and PC is set to Rs1. * ## RET {Rs1} * ## Rs1 can be a 64 bit general purpose register or XZR. * ## PC is set to Rs1, if no operand is given PC is set to X30. * ## CB(Z|NZ) Rs1, label * ## Rs1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. Rs1 can also be XZR or WZR. * ## If label is less than or equal to 1 megabyte away from PC and Rs1 is zero if the instruction is CBZ or not zero if the instruction is CBNZ then PC is set to label. * ## TB(Z|NZ) Rs1, imm1, label * ## Rs1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register. Rs1 can also be XZR or WZR. Now, imm1 can be 0 to m - 1. * ## If label is less than or equal to 32 kilobytes away from PC and bit imm1 of Rs1 is 0 if the instruction is TBZ or 1 if the instruction is TBNZ then PC is set to label. * ## CBcond Rs1, roi1, label * ## Rs1 and roi1 can be any 64 bit general purpose register or the lower 32 bits of any 64 bit general purpose register. They can also be XZR or WZR. They must share the same type if they are both registers. Also, roi1 can also be 0 to 63. This instruction does the comparison without changing NZCV. * ## cond can only be GT, GE, HI, HS, EQ, NE. * ## If label is less than or equal to 1 kilobyte away from PC and cond between Rs1 and roi1 is true then PC is set to label. * ## CBHcond Rs1, Rs2, label * ## Rs1 and Rs2 can be the lower 32 bits of a 64 bit general purpose register or WZR. This instruction does the comparison without changing NZCV. * ## cond can only be GT, GE, HI, HS, EQ, NE. * ## If label is less than or equal to 1 kilobyte away from PC and cond between the lower 16 bits of Rs1 and the lower 16 bits of Rs2 is true then PC is set to label. * ## CBBcond Rs1, Rs2, label * ## Rs1 and Rs2 can be the lower 32 bits of a 64 bit general purpose register or WZR. This instruction does the comparison without changing NZCV. * ## cond can only be GT, GE, HI, HS, EQ, NE. * ## If label is less than or equal to 1 kilobyte away from PC and cond between the lower 8 bits of Rs1 and the lower 8 bits of Rs2 is true then PC is set to label. # The Memory family ## The Memory family is the family that always reminds you of the fact that you broke their window or damaged their house in some way. * ## LDR{H|B|SW|SH|SB} Rd1, addr * ## Now, addr can be \[Rs1, {imm1}], \[Rsd1, imm1]!, \[Rsd1], imm1, or \[Rs1, Rs2, smf]. Rs1 and Rsd1 can both be a 64 bit general purpose register or SP for all of the possible forms of addr. * ## If addr is \[Rs1, {imm1}], imm1 is optional here, if it is not used it is equal to 0 and the following options are available for this form of addr. * ## If the instruction ends with no suffix then Rd1 can be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR or WZR and imm1 can be 0 to 32760 in multiples of 8 if Rd1 is a 64 bit general purpose register or XZR, or if Rd1 is the lower 32 bits of a 64 bit general purpose register or WZR then imm1 can be 0 to 16380 in multiples of 4. Rd1 will be set to the m bits at Rs1 plus imm1 being treated as an address. * ## If the instruction ends with H then imm1 can be 0 to 8190 in multiples of 2 and Rd1 must be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 16 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with B then imm1 can be 0 to 4095 and Rd1 must be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 8 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with SW then imm1 can be 0 to 16380 in multiples of 4 and Rd1 must be a 64 bit general purpose register or XZR. Rd1 will be set to 32 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at the address. * ## If the instruction ends with SH then imm1 can be 0 to 8190 in multiples of 2 and Rd1 can be a 64 bit general purpose register or XZR or the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 16 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to bit 15 of the bits at the address. * ## If the instruction ends with SB then imm1 can be 0 to 4095 and Rd1 can be a 64 bit general purpose register or XZR or the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 8 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to bit 7 of the bits at the address. * ## If addr is \[Rsd1, imm1]! then imm1 can be -256 to 255. Rsd1 will be increased by imm1 and Rd1 will be set to the bits at Rsd1. Rd1 will be set in certain ways depending on the following available options. * ## If the instruction ends with no suffix then Rd1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to m bits at Rsd1 being treated as an address. * ## If the instruction ends with H then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 16 bits at Rsd1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with B then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 8 bits at Rsd1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with SW then Rd1 can be a 64 bit general purpose register or XZR. Rd1 will be set to 32 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at the address. * ## If the instruction ends with SH then Rd1 can be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR, or WZR. Rd1 will be set to 16 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 15 of the bits at the address. * ## If the instruction ends with SB then Rd1 can be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR, or WZR. Rd1 will be set to 8 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 7 of the bits at the address. * ## If addr is \[Rsd1], imm1 then imm1 can be -256 to 255. Rd1 will be set to the bits at Rsd1 being treated as an address and then Rsd1 will be increased by imm1. Rd1 will be set in certain ways depending on the following available options. * ## If the instruction ends with no suffix then Rd1 can be a 64 bit general purpose register or XZR or the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to m bits at Rsd1 being treated as an address. * ## If the instruction ends with H then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 16 bits at Rsd1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with B then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to 8 bits at Rsd1 being treated as an address and the rest of Rd1 is set to 0. * ## If the instruction ends with SW then Rd1 can be a 64 bit general purpose register or XZR. Rd1 will be set to 32 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at the address. * ## If the instruction ends with SH then Rd1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register or XZR or WZR. Rd1 will be set to 16 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 15 of the bits at the address. * ## If the instruction ends with SB then Rd1 can be a 64 bit general purpose register or the lower 32 bits of a 64 bit general purpose register or XZR or WZR. Rd1 will be set to 8 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 7 of the bits at the address. * ## If addr is \[Rs1, Rs2, smf] then Rs2 is a 64 bit general purpose register or XZR or the lower 32 bits of a general purpose register or WZR, the following options are available. * ## If the instruction ends with no suffix then Rd1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. If Rd1 is a 64 bit general purpose register or XZR and Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 3, SXTX 0, or SXTX 3, if smf is not used then it is equal to LSL 0. If Rd1 is a 64 bit general purpose register or XZR and Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 3, UXTW 0, or UXTW 3. If Rd1 is the lower 32 bits of a 64 bit general purpose register or WZR and Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 2, SXTX 0, or SXTX 2, if smf is not used then it is equal to LSL 0. If Rd1 is the lower 32 bits of a 64 bit general purpose register or WZR and Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 2, UXTW 0, or UXTW 2. Rd1 will be set to m bits at Rs1 plus the result of smf applied to Rs2 being treated as an address. * ## If the instruction ends with H then Rd1 can be the lower 32 bits of a 64 bit general purpose register, if Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 1, SXTX 0, or SXTX 1, if smf is not used then it is equal to LSL 0. If Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 1, UXTW 0, or UXTW 1. Rd1 will be set to 16 bits at Rs1 plus the result of smf applied to Rs2 being treated as an address. * ## If the instruction ends with B then Rd1 can be the lower 32 bits of a 64 bit general purpose register, if Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0 or SXTX 0, if smf is not used then it is equal to LSL 0. If Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0 or UXTW 0. Rd1 will be set to 8 bits at Rs1 plus the result of smf applied to Rs2 being treated as an address. * ## If the instruction ends with SW then Rd1 can be a 64 bit general purpose register or XZR, if Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 2, SXTX 0, or SXTX 2, if smf is not used then it is equal to LSL 0. If Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 2, UXTW 0, or UXTW 2. Rd1 will be set to 32 bits at Rs1 plus the result of smf applied to Rs2 being treated as an address and the rest of Rd1 will be set to bit 31 of the bits at that address. * ## If the instruction ends with SH then Rd1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. If Rd1 is a 64 bit general purpose register or XZR or the lower 32 bits of a 64 bit general purpose register or WZR and Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 1, SXTX 0, or SXTX 1, if smf is not used then it is equal to LSL 0. Or if Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then must be SXTW 0, SXTW 1, UXTW 0, or UXTW 1. Rd1 will be set to 16 bits at Rs1 plus the result of smf applied to Rs2 being treated as an address, and the rest of Rd1 will be set to bit 15 of the bits at that address. * ## If the instruction ends with SB then Rd1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. If Rd1 is a 64 bit general purpose register or XZR or the lower 32 bits of a 64 bit general purpose register or WZR and Rs2 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0 or SXTX 0, if smf is not used then it is equal to LSL 0. Or if Rs2 is the lower 32 bits of a 64 bit general purpose register or WZR then must be SXTW 0 or UXTW 0. Rd1 will be set to 8 bits at Rs1 plus the result of smf applied to Rs2 being treated as an address, and the rest of Rd1 will be set to bit 7 of the bits at that address. * ## STR{H|B} Rs1, addr * ## Now, addr can be \[Rs2, {imm1}], \[Rsd1, imm1]!, \[Rsd1], imm1, or \[Rs2, Rs3, smf]. Rs2 and Rsd1 can both be a 64 bit general purpose register or SP for all of the address forms. * ## If addr is \[Rs2, {imm1}], imm1 is optional here, if it is not used it is equal to 0 and the following options are available for this form of addr. * ## If the instruction ends with no suffix then Rs1 can be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR or WZR and imm1 can be 0 to 32760 in multiples of 8 if Rs1 is a 64 bit general purpose register or XZR, or if Rs1 is the lower 32 bits of a 64 bit general purpose register or WZR then imm1 can be 0 to 16380 in multiples of 4. Rs2 plus imm1 being treated as an address is set to m bits at Rs1. * ## If the instruction ends with H then imm1 can be 0 to 8190 in multiples of 2 and Rs1 must be the lower 32 bits of a 64 bit general purpose register or WZR. Rs2 plus imm1 being treated as an address is set to 16 bits at Rs1. * ## If the instruction ends with B then imm1 can be 0 to 4095 and Rs1 must be the lower 32 bits of a 64 bit general purpose register or WZR. Rs2 plus imm1 being treated as an address is set to 8 bits at Rs1. * ## If addr is \[Rsd1, imm1]! then imm1 can be -256 to 255. Rsd1 will be increased by imm1 and Rsd1 being treated as an address will be set to a certain number of bits at Rs1 depending on the following available options. * ## If the instruction ends with no suffix then Rs1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to m bits at Rs1. * ## If the instruction ends with H then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to 16 bits at Rs1. * ## If the instruction ends with B then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to 8 bits at Rs1. * ## If addr is \[Rsd1], imm1 then imm1 can be -256 to 255. Rsd1 being treated as an address will be set to a certain number of bits at Rs1 depending on the following options and then Rsd1 will be increased by imm1. * ## If the instruction ends with no suffix then Rs1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to m bits at Rs1. * ## If the instruction ends with H then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to 16 bits at Rs1. * ## If the instruction ends with B then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rsd1 being treated as an address will be set to 8 bits at Rs1. * ## If addr is \[Rs2, Rs3, smf] then the following options are available. * ## If the instruction ends with no suffix then Rs1 can be a 64 bit general purpose register or XZR, or the lower 32 bits of a 64 bit general purpose register or WZR. If Rs1 is a 64 bit general purpose register or XZR and Rs3 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 3, SXTX 0, or SXTX 3, if smf is not used then it is equal to LSL 0. If Rs1 is a 64 bit general purpose register or XZR and Rs3 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 3, UXTW 0, or UXTW 3. If Rs1 is the lower 32 bits of a 64 bit general purpose register or WZR and Rs3 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 2, SXTX 0, or SXTX 2, if smf is not used then it is equal to LSL 0. If Rs1 is the lower 32 bits of a 64 bit general purpose register or WZR and Rs3 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 2, UXTW 0, or UXTW 2. Rs2 plus the result of smf applied to Rs3 being treated as an address will be set to m bits at Rs1. * ## If the instruction ends with H then Rs1 can be the lower 32 bits of a 64 bit general purpose register, if Rs3 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0, LSL 1, SXTX 0, or SXTX 1, if smf is not used then it is equal to LSL 0. If Rs3 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0, SXTW 1, UXTW 0, or UXTW 1. Rs2 plus the result of smf applied to Rs3 being treated as an address will be set to 16 bits at Rs1. * ## If the instruction ends with B then Rs1 can be the lower 32 bits of a 64 bit general purpose register, if Rs3 is a 64 bit general purpose register or XZR then smf is optional and can be LSL 0 or SXTX 0, if smf is not used then it is equal to LSL 0. If Rs3 is the lower 32 bits of a 64 bit general purpose register or WZR then smf must be SXTW 0 or UXTW 0. Rs2 plus the result of smf applied to Rs3 being treated as an address will be set to 8 bits at Rs1. * ## LDUR{H|B|SW|SH|SB} Rd1, addr * ## addr can be \[Rs1, {imm1}] with Rs1 being a 64 bit general purpose register or SP, and imm1 being -256 to 255, imm1 is optional here, if it is not used it is equal to 0. * ## If the instruction ends with no suffix then Rd1 can be a 64 bit general purpose register, XZR, the lower 32 bits of a 64 bit general purpose register, or WZR. Rd1 will be set to the m bits at Rs1 plus imm1 being treated as an address. * ## If the instruction ends with H then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to the 16 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 will be set to 0. * ## If the instruction ends with B then Rd1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rd1 will be set to the 8 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 will be set to 0. * ## If the instruction ends with SW then Rd1 can be a 64 bit general purpose register or XZR. Rd1 will be set to the 32 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 will be set to bit 31 of the bits at Rs1 plus imm1. * ## If the instruction ends with SH then Rd1 can be a 64 bit general purpose register, XZR, the lower 32 bits of a 64 bit general purpose register, or WZR. Rd1 will be set to the 16 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 will be set to bit 15 at Rs1 plus imm1. * ## If the instruction ends with SB then Rd1 can be a 64 bit general purpose register, XZR, the lower 32 bits of a 64 bit general purpose register, or WZR. Rd1 will be set to the 8 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 will be set to bit 7 at Rs1 plus imm1. * ## STUR{H|B} Rs1, addr * ## addr can be \[Rs2, {imm1}] with Rs2 being a 64 bit general purpose register or SP, and imm1 being -256 to 255, imm1 is optional here, if it is not used it is equal to 0. * ## If the instruction ends with no suffix then Rs1 can be a 64 bit general purpose register, XZR, the lower 32 bits of a 64 bit general purpose register, or WZR. Rs2 plus imm1 being treated as an address will be set to m bits at Rs1. * ## If the instruction ends with H then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rs2 plus imm1 being treated as an address will be set to 16 bits at Rs1. * ## If the instruction ends with B then Rs1 can be the lower 32 bits of a 64 bit general purpose register or WZR. Rs2 plus imm1 being treated as an address will be set to 8 bits at Rs1. * ## LDP{SW} Rd1, Rd2, addr * ## Now, addr can be \[Rs1, {imm1}], \[Rsd1, imm1]!, or \[Rsd1], imm1. Rs1 and Rsd1 can both be a 64 bit general purpose register or SP for all of the address forms. Both Rd1 and Rd2 cant be the same and Rsd1 cannot be either Rd1 or Rd2. Rd1 and Rd2 must be the same type. If the instruction ends with no suffix then Rd1 and Rd2 can both be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR or WZR and imm1 can be -512 to 504 in multiples of 8 if Rd1 is a 64 bit general purpose register or XZR, or if Rd1 is the lower 32 bits of a 64 bit general purpose register or WZR then imm1 can be -256 to 252 in multiples of 4. If the instruction ends with SW then Rd1 and Rd2 can either be a 64 bit general purpose register or XZR and imm1 can be -256 to 252 in multiples of 4. Now if addr is \[Rs1, {imm1}] then imm1 is optional here, if it is not used it is equal to 0. * ## If addr is \[Rs1, {imm1}] then the following options are available. * ## If the instruction ends with no suffix then Rd1 is set to m bits at Rs1 plus imm1 being treated as an address and Rd2 is set to m bits at Rs1 plus imm1 plus m divided by 8 being treated as an address. * ## If the instruction ends with SW then Rd1 is set to 32 bits at Rs1 plus imm1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at Rs1 plus imm1 being treated as an address and Rd2 is set to 32 bits at Rs1 plus imm1 plus 4 being treated as an address and the rest of Rd2 is set to bit 31 of the bits at Rs1 plus imm1 plus 4 being treated as an address. * ## If addr is \[Rsd1, imm1]! then Rsd1 will be increased by imm1 and the following options are available. * ## If the instruction ends with no suffix then Rd1 will be set to m bits at Rsd1 being treated as an address and Rd2 will be set to m bits at Rsd1 plus m divided by 8 being treated as an address. * ## If the instruction ends with SW then Rd1 will be set to 32 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at Rsd1 being treated as an address and Rd2 will be set to 32 bits at Rsd1 plus 4 being treated as an address and the rest of Rd2 is set to bit 31 of the bits at Rsd1 plus 4 being treated as an address. * ## If addr is \[Rsd1], imm1 then Rd1 and Rd2 will be set and then Rsd1 will be increased by imm1 and the following options are available for how Rd1 and Rd2 are set. * ## If the instruction ends with no suffix then Rd1 will be set to m bits at Rsd1 being treated as an address and Rd2 will be set to m bits at Rsd1 plus m divided by 8 being treated as an address. * ## If the instruction ends with SW then Rd1 will be set to 32 bits at Rsd1 being treated as an address and the rest of Rd1 is set to bit 31 of the bits at Rsd1 being treated as an address and Rd2 will be set to 32 bits at Rsd1 plus 4 being treated as an address and the rest of Rd2 is set to bit 31 of the bits at Rsd1 plus 4 being treated as an address. * ## STP Rs1, Rs2, addr * ## Now, addr can be \[Rs3, {imm1}], \[Rsd1, imm1]!, or \[Rsd1], imm1. Rs3 and Rsd1 can both be a 64 bit general purpose register or SP for all of the address forms. Rs1 and Rs2 must be the same type. Rs1 and Rs2 can both be a 64 bit general purpose register, the lower 32 bits of a 64 bit general purpose register, XZR or WZR and imm1 can be -512 to 504 in multiples of 8 if Rs1 is a 64 bit general purpose register or XZR, or if Rs1 is the lower 32 bits of a 64 bit general purpose register or WZR then imm1 can be -256 to 252 in multiples of 4. If addr is either \[Rsd1, imm1]! or \[Rsd1], imm1 then Rsd1 cant be the same as either Rs1 or Rs2. Now if addr is \[Rs3, {imm1}] then imm1 is optional here, if it is not used it is equal to 0. * ## If addr is \[Rs3, {imm1}] then Rs3 plus imm1 treated as an address is set to m bits at Rs1 and Rs3 plus imm1 plus m divided by 8 treated as an address is set to m bits at Rs2. * ## If addr is \[Rsd1, imm1]! then Rsd1 will be increased by imm1 and then Rsd1 treated as an address is set to m bits at Rs1 and Rsd1 plus m divided by 8 treated as an address is set to m bits at Rs2. * ## If addr is \[Rsd1], imm1 then Rsd1 being treated as an address will be set to m bits at Rs1 and Rsd1 plus m divided by 8 treated as an address is set to m bits at Rs2 and then Rsd1 will be increased by imm1. * ## LDNP Rd1, Rd2, \[Rs1, imm1] * ## STNP Rs1, Rs2, \[Rs3, imm1] * ## ADR{P} Rd1, label * ## LDTR Rd1, \[Rs1, imm1] * ## LDTRH Rd1, \[Rs1, imm1] * ## LDTRB Rd1, \[Rs1, imm1] * ## LDTRSW Rd1, \[Rs1, imm1] * ## LDTRSH Rd1, \[Rs1, imm1] * ## LDTRSB Rd1, \[Rs1, imm1] * ## STTR Rs1, \[Rs2, imm1] * ## STTRH Rs1, \[Rs2, imm1] * ## STTRB Rs1, \[Rs2, imm1] * ## LDXR Rd1, \[Rs1] * ## LDXRH Rd1, \[Rs1] * ## LDXRB Rd1, \[Rs1] * ## LDXP Rd1, Rd2, \[Rs1] * ## STXR Rs1, Rs2, \[Rs3] * ## STXRH Rs1, Rs2, \[Rs3] * ## STXRB Rs1, Rs2, \[Rs3] * ## STXP Rs1, Rs2, Rs3, \[Rs4] * ## LDAR Rd1, \[Rs1] * ## LDARH Rd1, \[Rs1] * ## LDARB Rd1, \[Rs1] * ## LDAPUR Rd1, \[Rs1, imm1] * ## LDAPURH Rd1, \[Rs1, imm1] * ## LDAPURB Rd1, \[Rs1, imm1] * ## LDAPURSW Rd1, \[Rs1, imm1] * ## LDAPURSH Rd1, \[Rs1, imm1] * ## LDAPURSB Rd1, \[Rs1, imm1] * ## STLUR Rs1, \[Rs2, imm1] * ## STLURH Rs1, \[Rs2, imm1] * ## STLURB Rs1, \[Rs2, imm1] * ## PRFM prf, label * ## PRFM prf, \[Rs1, smf] * ## PRFM prf, \[Rs1, imm1] * ## PRFUM prf, \[Rs1, imm1] * ## RPRFM imm1, Rs1, \[Rs2] * ## LDIAPP Rd1, Rd2, \[Rs1] * ## STILP Rs1, Rs2, \[Rs3] * ## STLR Rs1, \[Rs2] * ## STLRH Rs1, \[Rs2] * ## STLRB Rs1, \[Rs2] * ## LDAXR Rd1, \[Rs1] * ## LDAXRH Rd1, \[Rs1] * ## LDAXRB Rd1, \[Rs1] * ## STLXR Rs1, Rs2, \[Rs3] * ## STLXRH Rs1, Rs2, \[Rs3] * ## STLXRB Rs1, Rs2, \[Rs3] * ## LDAXP Rd1, Rd2, \[Rs1] * ## STLXP Rs1, Rs2, Rs3, \[Rs4] * ## SWP Rs1, Rd1, \[Rs2] * ## SWPH Rs1, Rd1, \[Rs2] * ## SWPB Rs1, Rd1, \[Rs2] * ## SWPA Rs1, Rd1, \[Rs2] * ## SWPAH Rs1, Rd1, \[Rs2] * ## SWPAB Rs1, Rd1, \[Rs2] * ## SWPL Rs1, Rd1, \[Rs2] * ## SWPLH Rs1, Rd1, \[Rs2] * ## SWPLB Rs1, Rd1, \[Rs2] * ## SWPAL Rs1, Rd1, \[Rs2] * ## SWPALH Rs1, Rd1, \[Rs2] * ## SWPALB Rs1, Rd1, \[Rs2] * ## CAS Rsd1, Rs1, \[Rs2] * ## CASH Rsd1, Rs1, \[Rs2] * ## CASB Rsd1, Rs1, \[Rs2] * ## CASA Rsd1, Rs1, \[Rs2] * ## CASAH Rsd1, Rs1, \[Rs2] * ## CASAB Rsd1, Rs1, \[Rs2] * ## CASL Rsd1, Rs1, \[Rs2] * ## CASLH Rsd1, Rs1, \[Rs2] * ## CASLB Rsd1, Rs1, \[Rs2] * ## CASAL Rsd1, Rs1, \[Rs2] * ## CASALH Rsd1, Rs1, \[Rs2] * ## CASALB Rsd1, Rs1, \[Rs2] * ## CASP Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPA Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPL Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPAL Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CPYFP \[Rs1]!, \[Rs2]!, Rs3! * ## CPYFM \[Rs1]!, \[Rs2]!, Rs3! * ## CPYFE \[Rs1]!, \[Rs2]!, Rs3! * ## CPYP \[Rs1]!, \[Rs2]!, Rs3! * ## CPYM \[Rs1]!, \[Rs2]!, Rs3! * ## CPYE \[Rs1]!, \[Rs2]!, Rs3! * ## SETP \[Rs1]!, Rs2!, Rs3 * ## SETM \[Rs1]!, Rs2!, Rs3 * ## SETE \[Rs1]!, Rs2!, Rs3 * ## SETGP \[Rs1]!, Rs2!, Rs3 * ## SETGM \[Rs1]!, Rs2!, Rs3 * ## SETGE \[Rs1]!, Rs2!, Rs3 * ## LDADD Rs1, Rd1, \[Rs2] * ## LDADDH Rs1, Rd1, \[Rs2] * ## LDADDB Rs1, Rd1, \[Rs2] * ## LDADDA Rs1, Rd1, \[Rs2] * ## LDADDAH Rs1, Rd1, \[Rs2] * ## LDADDAB Rs1, Rd1, \[Rs2] * ## LDADDL Rs1, Rd1, \[Rs2] * ## LDADDLH Rs1, Rd1, \[Rs2] * ## LDADDLB Rs1, Rd1, \[Rs2] * ## LDADDAL Rs1, Rd1, \[Rs2] * ## LDADDALH Rs1, Rd1, \[Rs2] * ## LDADDALB Rs1, Rd1, \[Rs2] * ## LDCLR Rs1, Rd1, \[Rs2] * ## LDCLRH Rs1, Rd1, \[Rs2] * ## LDCLRB Rs1, Rd1, \[Rs2] * ## LDCLRA Rs1, Rd1, \[Rs2] * ## LDCLRAH Rs1, Rd1, \[Rs2] * ## LDCLRAB Rs1, Rd1, \[Rs2] * ## LDCLRL Rs1, Rd1, \[Rs2] * ## LDCLRLH Rs1, Rd1, \[Rs2] * ## LDCLRLB Rs1, Rd1, \[Rs2] * ## LDCLRAL Rs1, Rd1, \[Rs2] * ## LDCLRALH Rs1, Rd1, \[Rs2] * ## LDCLRALB Rs1, Rd1, \[Rs2] * ## LDSET Rs1, Rd1, \[Rs2] * ## LDSETH Rs1, Rd1, \[Rs2] * ## LDSETB Rs1, Rd1, \[Rs2] * ## LDSETA Rs1, Rd1, \[Rs2] * ## LDSETAH Rs1, Rd1, \[Rs2] * ## LDSETAB Rs1, Rd1, \[Rs2] * ## LDSETL Rs1, Rd1, \[Rs2] * ## LDSETLH Rs1, Rd1, \[Rs2] * ## LDSETLB Rs1, Rd1, \[Rs2] * ## LDSETAL Rs1, Rd1, \[Rs2] * ## LDSETALH Rs1, Rd1, \[Rs2] * ## LDSETALB Rs1, Rd1, \[Rs2] * ## LDEOR Rs1, Rd1, \[Rs2] * ## LDEORH Rs1, Rd1, \[Rs2] * ## LDEORB Rs1, Rd1, \[Rs2] * ## LDEORA Rs1, Rd1, \[Rs2] * ## LDEORAH Rs1, Rd1, \[Rs2] * ## LDEORAB Rs1, Rd1, \[Rs2] * ## LDEORL Rs1, Rd1, \[Rs2] * ## LDEORLH Rs1, Rd1, \[Rs2] * ## LDEORLB Rs1, Rd1, \[Rs2] * ## LDEORAL Rs1, Rd1, \[Rs2] * ## LDEORALH Rs1, Rd1, \[Rs2] * ## LDEORALB Rs1, Rd1, \[Rs2] * ## LDSMAX Rs1, Rd1, \[Rs2] * ## LDSMAXA Rs1, Rd1, \[Rs2] * ## LDSMAXL Rs1, Rd1, \[Rs2] * ## LDSMAXAL Rs1, Rd1, \[Rs2] * ## LDSMIN Rs1, Rd1, \[Rs2] * ## LDSMINA Rs1, Rd1, \[Rs2] * ## LDSMINL Rs1, Rd1, \[Rs2] * ## LDSMINAL Rs1, Rd1, \[Rs2] * ## Rs1 must be a 64 bit general purpose register or XZR while Rd1 must be a 64 bit general purpose register. Rs2 must be a 64 bit general purpose register or SP. * ## LDUMAX Rs1, Rd1, \[Rs2] * ## LDUMAXA Rs1, Rd1, \[Rs2] * ## LDUMAXL Rs1, Rd1, \[Rs2] * ## LDUMAXAL Rs1, Rd1, \[Rs2] * ## LDUMIN Rs1, Rd1, \[Rs2] * ## LDUMINA Rs1, Rd1, \[Rs2] * ## LDUMINL Rs1, Rd1, \[Rs2] * ## LDUMINAL Rs1, Rd1, \[Rs2] * ## SWPP Rd1, Rd2, \[Rs1] * ## SWPPA Rd1, Rd2, \[Rs1] * ## SWPPL Rd1, Rd2, \[Rs1] * ## SWPPAL Rd1, Rd2, \[Rs1] * ## LDCLRP Rd1, Rd2, \[Rs1] * ## LDCLRPA Rd1, Rd2, \[Rs1] * ## LDCLRPL Rd1, Rd2, \[Rs1] * ## LDCLRPAL Rd1, Rd2, \[Rs1] * ## LDSETP Rd1, Rd2, \[Rs1] * ## LDSETPA Rd1, Rd2, \[Rs1] * ## LDSETPL Rd1, Rd2, \[Rs1] * ## LDSETPAL Rd1, Rd2, \[Rs1] * ## LDAPR Rd1, \[Rs1] * ## LDAPRH Rd1, \[Rs1] * ## LDAPRB Rd1, \[Rs1] * ## LDLAR Rd1, \[Rs1] * ## LDLARH Rd1, \[Rs1] * ## LDLARB Rd1, \[Rs1] * ## STLLR Rs1, \[Rs2] * ## STLLRH Rs1, \[Rs2] * ## STLLRB Rs1, \[Rs2] * ## LDTADD Rs1, Rd1, \[Rs2] * ## LDTADDA Rs1, Rd1, \[Rs2] * ## LDTADDL Rs1, Rd1, \[Rs2] * ## LDTADDAL Rs1, Rd1, \[Rs2] * ## LDTCLR Rs1, Rd1, \[Rs2] * ## LDTCLRA Rs1, Rd1, \[Rs2] * ## LDTCLRL Rs1, Rd1, \[Rs2] * ## LDTCLRAL Rs1, Rd1, \[Rs2] * ## LDTSET Rs1, Rd1, \[Rs2] * ## LDTSETA Rs1, Rd1, \[Rs2] * ## LDTSETL Rs1, Rd1, \[Rs2] * ## LDTSETAL Rs1, Rd1, \[Rs2] * ## SWPT Rs1, Rd1, \[Rs2] * ## SWPTA Rs1, Rd1, \[Rs2] * ## SWPTL Rs1, Rd1, \[Rs2] * ## SWPTAL Rs1, Rd1, \[Rs2] * ## CAST Rsd1, Rs1, \[Rs2] * ## CASAT Rsd1, Rs1, \[Rs2] * ## CASLT Rsd1, Rs1, \[Rs2] * ## CASALT Rsd1, Rs1, \[Rs2] * ## CASPT Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPAT Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPLT Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## CASPALT Rsd1, Rsd2, Rs1, Rs2, \[Rs3] * ## LDTP Rd1, Rd2, \[Rs1, imm1] * ## LDTNP Rd1, Rd2, \[Rs1, imm1] * ## STTP Rd1, Rd2, \[Rs1, imm1] * ## STTNP Rd1, Rd2, \[Rs1, imm1] * ## LDTXR Rd1, \[Rs1] * ## LDATXR Rd1, \[Rs1] * ## STTXR Rs1 ,Rs2, \[Rs3] * ## STLTXR Rs1, Rs2, \[Rs3] * ## LDSMAXB Rs1, Rd1, \[Rs2] * ## LDSMAXAB Rs1, Rd1, \[Rs2] * ## LDSMAXLB Rs1, Rd1, \[Rs2] * ## LDSMAXALB Rs1, Rd1, \[Rs2] * ## LDSMAXH Rs1, Rd1, \[Rs2] * ## LDSMAXAH Rs1, Rd1, \[Rs2] * ## LDSMAXLH Rs1, Rd1, \[Rs2] * ## LDSMAXALH Rs1, Rd1, \[Rs2] * ## LDSMINB Rs1, Rd1, \[Rs2] * ## LDSMINAB Rs1, Rd1, \[Rs2] * ## LDSMINLB Rs1, Rd1, \[Rs2] * ## LDSMINALB Rs1, Rd1, \[Rs2] * ## LDSMINH Rs1, Rd1, \[Rs2] * ## LDSMINAH Rs1, Rd1, \[Rs2] * ## LDSMINLH Rs1, Rd1, \[Rs2] * ## LDSMINALH Rs1, Rd1, \[Rs2] * ## LDUMAXB Rs1, Rd1, \[Rs2] * ## LDUMAXAB Rs1, Rd1, \[Rs2] * ## LDUMAXLB Rs1, Rd1, \[Rs2] * ## LDUMAXALB Rs1, Rd1, \[Rs2] * ## LDUMAXH Rs1, Rd1, \[Rs2] * ## LDUMAXAH Rs1, Rd1, \[Rs2] * ## LDUMAXLH Rs1, Rd1, \[Rs2] * ## LDUMAXALH Rs1, Rd1, \[Rs2] * ## LDUMINB Rs1, Rd1, \[Rs2] * ## LDUMINAB Rs1, Rd1, \[Rs2] * ## LDUMINLB Rs1, Rd1, \[Rs2] * ## LDUMINALB Rs1, Rd1, \[Rs2] * ## LDUMINH Rs1, Rd1, \[Rs2] * ## LDUMINAH Rs1, Rd1, \[Rs2] * ## LDUMINLH Rs1, Rd1, \[Rs2] * ## LDUMINALH Rs1, Rd1, \[Rs2] * ## RCWCAS Rsd1, Rs1, \[Rs2] * ## RCWCASA Rsd1, Rs1, \[Rs2] * ## RCWCASL Rsd1, Rs1, \[Rs2] * ## RCWCASAL Rsd1, Rs1, \[Rs2] * ## RCWCLR Rsd1, Rs1, \[Rs2] * ## RCWCLRA Rsd1, Rs1, \[Rs2] * ## RCWCLRL Rsd1, Rs1, \[Rs2] * ## RCWCLRAL Rsd1, Rs1, \[Rs2] * ## RCWSET Rsd1, Rs1, \[Rs2] * ## RCWSETA Rsd1, Rs1, \[Rs2] * ## RCWSETL Rsd1, Rs1, \[Rs2] * ## RCWSETAL Rsd1, Rs1, \[Rs2] * ## RCWSWP Rsd1, Rs1, \[Rs2] * ## RCWSWPA Rsd1, Rs1, \[Rs2] * ## RCWSWPL Rsd1, Rs1, \[Rs2] * ## RCWSWPAL Rsd1, Rs1, \[Rs2] * ## LD64B Rd1, \[Rs1] * ## LD64B Rs1, \[Rs1] * ## ST64BV Rd1, Rs1, \[Rs2] * ## ST64BV0 Rd1, Rs1, \[Rs2] # The PointerAuthentication family * ## PACM * ## PACIASPPC * ## PACIBSPPC * ## AUTIASPPC label * ## AUTIBSPPC label * ## AUTIASPPCR Rs1 * ## AUTIBSPPCR Rs1 * ## RETAASPPC label * ## RETABSPPC label * ## RETAASPPCR Rs1 * ## RETABSPPCR Rs1 * ## PACNBIASPPC * ## PACNBIBSPPC * ## PACIA171615 * ## PACIB171615 * ## AUTIA171615 * ## AUTIB171615 * ## PACIA Rd1, Rs1 * ## PACIB Rd1, Rs1 * ## PACDA Rd1, Rs1 * ## PACDB Rd1, Rs1 * ## PACIZA Rd1 * ## PACIZB Rd1 * ## PACDZA Rd1 * ## PACDZB Rd1 * ## PACIA1716 * ## PACIB1716 * ## PACIASP * ## PACIBSP * ## PACIAZ * ## PACIBZ * ## AUTIA Rd1, Rs1 * ## AUTIB Rd1, Rs1 * ## AUTDA Rd1, Rs1 * ## AUTDB Rd1, Rs1 * ## AUTIZA Rd1 * ## AUTIZB Rd1 * ## AUTDZA Rd1 * ## AUTDZB Rd1 * ## PACGA Rd1, Rs1, Rs2 * ## AUTIA1716 * ## AUTIB1716 * ## AUTIASP * ## AUTIBSP * ## AUTIAZ * ## AUTIBZ * ## XPACI Rd1 * ## XPACD Rd1 * ## XPACLRI * ## RETAA * ## RETAB * ## BRAA Rs1, Rs2 * ## BRAB Rs1, Rs2 * ## BLRAA Rs1, Rs2 * ## BLRAB Rs1, Rs2 * ## BRAAZ Rs1 * ## BRABZ Rs1 * ## BLRAAZ Rs1 * ## BLRABZ Rs1 * ## LDRAA Rd1, \[Rs1, imm1] * ## LDRAA Rd1, \[Rs1, imm1]! * ## LDRAB Rd1, \[Rs1, imm1] * ## LDRAB Rd1, \[Rs1, imm1]! * ## ERETAA * ## ERETAB # The MemoryTagging family * ## IRG Rd1, Rs1, Rs2 * ## GMI Rd1, Rs1, Rs2 * ## ADDG Rd1, Rs1, imm1, imm2 * ## SUBG Rd1, Rs1, imm1, imm2 * ## SUBP Rd1, Rs1, Rs2 * ## SUBPS Rd1, Rs1, Rs2 * ## STG Rs1, \[Rs2, imm1] * ## STG Rs1, \[Rs2, imm1]! * ## STG Rs1, \[Rs2], imm1 * ## STZG Rs1, \[Rs2, imm1] * ## STZG Rs1, \[Rs2, imm1]! * ## STZG Rs1, \[Rs2], imm1 * ## ST2G Rs1, \[Rs2, imm1] * ## ST2G Rs1, \[Rs2, imm1]! * ## ST2G Rs1, \[Rs2], imm1 * ## STZ2G Rs1, \[Rs2, imm1] * ## STZ2G Rs1, \[Rs2, imm1]! * ## STZ2G Rs1, \[Rs2], imm1 * ## STGP Rs1, Rs2, \[Rs3, imm1] * ## STGP Rs1, Rs2, \[Rs3, imm1]! * ## STGP Rs1, Rs2, \[Rs3], imm1 * ## LDG Rd1, \[Rs1, imm1] * ## STGM Rs1, \[Rs2] * ## STZGM Rs1, \[Rs2] * ## LDGM Rd1, \[Rs1] # The stack guard family * ## GCSPUSHM Rs1 * ## GCSPOPM Rd1 * ## GCSPUSHX * ## GCSPOPX * ## GCSPOPCX * ## GCSSS1 Rs1 * ## GCSSS2 Rd1 * ## GCSSTR Rs1, \[Rs2] * ## GCSSTTR Rs1, \[Rs2] * ## GCSB DSYNC # The flag manipulation family * ## CFINV * ## The carry flag is inverted. * ## RMIF Rs1, imm1, imm2 * ## Rs1 must be a 64 bit general purpose register or XZR. * ## imm1 must be 0 to 63. * ## imm2 must be 0 to 15. * ## SETF8 * ## Rs1 must be a the lower 32 bits of a 64 bit general purpose register or WZR. * ## SETF16 * ## Rs1 must be a the lower 32 bits of a 64 bit general purpose register or WZR. # The Crc family * ## CRC32B Rd1, Rs1, Rs2 * ## CRC32H Rd1, Rs1, Rs2 * ## CRC32W Rd1, Rs1, Rs2 * ## CRC32X Rd1, Rs1, Rs2 * ## CRC32CB Rd1, Rs1, Rs2 * ## CRC32CH Rd1, Rs1, Rs2 * ## CRC32CW Rd1, Rs1, Rs2 * ## CRC32CX Rd1, Rs1, Rs2 # The System family ## The System family is the family that is in charge of the overall neighborhood. * ## HINT imm1 * ## DMB opt1 * ## DSB opt1 * ## ISB opt1 * ## MRS Rd1, sysreg * ## MSR sysreg, Rs1 * ## MSR pstate, imm1 * ## SYS imm1, Cs1, Cs2, imm2, Rs1 * ## SYSL Rd1, imm1, Cs1, Cs2, imm2 * ## SVC imm1 * ## HVC imm1 * ## SMC imm1 * ## BRK imm1 * ## HLT imm1 * ## CLREX